A few days ago, we looked at the power costs associated with moving data on some desktop parts. This is a short follow up with some data from Zen 3 and Willow Cove in mobile configurations, as well as Cascade Lake-X. That lets us dig into how power costs…

We often see very high clock frequencies listed for our CPUs. But CPUs don’t run at maximum clock all the time in order to reduce power consumption and heat generation. They also can’t instantly go from one clock speed to another, because power delivery circuitry…

Processor caches are known to improve performance, but they also significantly influence power efficiency. Modern CPUs spend a lot of power to move data around. If data can be pulled from sources closer to the core, the CPU can spend less power moving data.…

If there’s one thing that’s cheaper than building a new fab, it’s expanding an existing one. Intel’s Oregon D1 facility has been the hub of all of its technology advancements over the past 20 years, whereby Intel will trial new manufacturing processes before…

The three main architectures currently in the ecosystem that people talk about are x86, Arm, and RISC-V. It’s that last one we’re focusing on, as the newest on the block and it is slowly becoming a de-facto option for a lot of simple compute designs as well…

Centaur’s CHA chip targets the server market with a low core count. Its dual socket capability is therefore quite important, because it’d allow up to 16 cores in a single CHA-based server. Unfortunately for Centaur, modern dual socket implementations are…

Figuring out the best way to encode a video is very computationally expensive, and it might not a good idea to throw a ton of CPU cycles at encoding video when you’re running a game. That’s why modern GPUs usually include hardware video encoders. Here, we’ll…

Reviews across the internet show Alder Lake getting very competitive performance with very high power consumption. For example, Anandtech measured 272 W of package power during a POV-Ray run. Our own testing showed eight Golden Cove cores alone could pull…

This is the deeper dive of AMD’s V-Cache that we teased with our short latency article and we will be covering a little more on the latency front along with the bandwidth behavior of V-Cache and the performance of V-Cache SKUs. A Bit More on Latency If you…

This will be a short post about how Alder Lake’s ring behaves when E-Cores are active. With just P-Cores active, the ring runs at 4.7 GHz. But if anything is running on the E-Cores, the ring frequency drops to 3.6 GHz. This drop happens regardless of whether…

If you were like us and were surprised that AMD announced 3D V-Cache back in August and wondered how AMD would be able to pull this off, well, we have a teaser article for you today regarding V-Cache’s latency! The Latency There was much speculation about…

I’ll be blunt here, this part will seem like an anti-climax compared to Part 2 of this series but I hope to nicely wrap up this series with this as the conclusion piece of what we know about how the changes talked about in Part 2 have affected the performance…

While chronic GPU shortages dominate the current news cycle (exacerbated by a myriad of individual factors set to continue for the foreseeable future), the massive increase in power requirements for high-end graphics cards is just as newsworthy. These higher…

While most enthusiasts chase the absolute best performance at any cost, there are a few who use efficiency as their benchmark for a card’s attractiveness. It can be argued that the efficiency of a design – how effectively it utilizes the resources available…

Header Image credit goes to Martijn Boer. In the world of x86 CPUs there are two major players, Intel and AMD. However, there is one (well two but that will be expanded on later) other company that designs and produces CPUs that are fully compatible with…

Often using an older GPU means sacrificing visual quality or resolution—trade-offs that many may find to be unacceptable. Overclocking can help of course, but what if you want more?That, my friends, is what we are here to find out.

Author’s Note: Andrei Frumusanu from Anandtech has reached out in this Tweet to clarify how Anandtech does Core to Core latency testing https://twitter.com/andreif7/status/1373942191920406530?s=19 Now, the program we use for Core to Core testing was made…

Banner image credit goes to Fritzchens Fritz and his amazing die shots Recent AMD and Intel high performance CPUs implement an op cache that remembers decoder output and functions like a L0 instruction cache. Compared to the traditional L1i fetch and decode…

Previously, we looked at ARM and x86 and concluded high performance designs wouldn’t get a significant advantage by using either instruction set. That article focused narrowly on the respective ISAs, and assumed equal ecosystem and implementation goals. Today…

Zen 3 is one of the fastest CPU cores currently on the market; that isn’t up for debate.However, even the fastest CPU cores have bottlenecks and today we are talking about the bottlenecks that Zen 3 has and what AMD could improve with Zen 4. We gathered far…